Semiconductor wafers containing integrated circuits separated by saw lanes may have metalized structures such as test components in the saw lanes. The metallized structures may include interconnect leads and probe pads in dielectric layers. During a saw process which separates the integrated circuits, metal from the metalized structures may cause short circuit defects at edges of the integrated circuits. Cracks and chips in the dielectric layers resulting from the sawing process may also cause defects at the edges of the integrated circuits.